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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 32: Block RAM and FIFO Switching Characteristics (Cont’d)
Speed Grade
Symbol
Description
1.0V
0.9V
Units
-3
-2/-2L
-1
-1M
-2L
T RCCK_INJECTBITERR /
T RCKC_INJECTBITERR
T RCCK_EN /T RCKC_EN
T RCCK_REGCE /T RCKC_REGCE
Inject single/double bit error in
ECC mode
Block RAM Enable (EN) input
CE input of output register
0.49/0.30
0.30/0.17
0.21/0.13
0.55/0.31
0.33/0.18
0.25/0.13
0.63/0.34
0.38/0.20
0.31/0.14
0.63/0.43
0.38/0.32
0.31/0.19
0.78/0.41
0.48/0.22
0.34/0.16
ns, Min
ns, Min
ns, Min
T RCCK_RSTREG /T RCKC_RSTREG Synchronous RSTREG input
T RCCK_RSTRAM /T RCKC_RSTRAM Synchronous RSTRAM input
0.25/0.06
0.27/0.35
0.27/0.06
0.29/0.37
0.29/0.06
0.31/0.39
0.29/0.14
0.31/0.39
0.35/0.06
0.34/0.40
ns, Min
ns, Min
T RCCK_WEA /T RCKC_WEA
T RCCK_WREN /T RCKC_WREN
T RCCK_RDEN /T RCKC_RDEN
Write Enable (WE) input (Block
RAM only)
WREN FIFO inputs
RDEN FIFO inputs
0.38/0.15
0.39/0.25
0.36/0.26
0.41/0.16
0.39/0.30
0.36/0.30
0.46/0.17
0.40/0.37
0.37/0.37
0.46/0.29
0.40/0.49
0.37/0.49
0.54/0.19
0.65/0.37
0.60/0.38
ns, Min
ns, Min
ns, Min
Reset Delays
T RCO_FLAGS
Reset RST to FIFO
flags/pointers (10)
0.76
0.83
0.93
0.93
1.06
ns, Max
T RREC_RST /T RREM_RST
Maximum Frequency
FIFO reset recovery and removal 1.59/–0.68 1.76/–0.68 2.01/–0.68 2.01/–0.68 2.07/–0.60 ns, Max
timing (11)
F MAX_BRAM_WF_NC
Block RAM
(Write first and No change
601.32
543.77
458.09
458.09
372.44
MHz
modes)
When not in SDP RF mode
F MAX_BRAM_RF_PERFORMANCE
Block RAM
(Read first, Performance mode)
601.32
543.77
458.09
458.09
372.44
MHz
When in SDP RF mode but no
address overlap between port A
and port B
F MAX_BRAM_RF_DELAYED_WRITE Block RAM
(Read first, Delayed_write mode)
528.26
477.33
400.80
400.80
317.36
MHz
When in SDP RF mode and
there is possibility of overlap
between port A and port B
addresses
F MAX_CAS_WF_NC
Block RAM Cascade
(Write first, No change mode)
551.27
493.83
408.00
408.00
322.48
MHz
When cascade but not in RF
mode
F MAX_CAS_RF_PERFORMANCE
Block RAM Cascade
(Read first, Performance mode)
551.27
493.83
408.00
408.00
322.48
MHz
When in cascade with RF mode
and no possibility of address
overlap/one port is disabled
F MAX_CAS_RF_DELAYED_WRITE
When in cascade RF mode and
there is a possibility of address
478.24
427.35
350.88
350.88
267.38
MHz
overlap between port A and port
B
DS182 (v2.8) March 4, 2014
Product Specification
www.xilinx.com
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